/*output module connected to an input module using a credit based flow contorl*/



module inputPort (data_in, credits_out, CLOCK_50)
	queue Q (.clock(CLOCK_50), data_in, valid_in, ready_out, data_out, valid_out, ready_in(1'b1))
	always @(posedge CLOCK_50)
	begin
		credits_out <= (valid_out)? 1'b1:1b0;
	end
	/* how do we do the logic for determining if data_in is valid data or nothing? */
	/* valid signal? */
	
	
		
endmodule





module channel (CLOCK_50, data_in, data_out)

always @(posedge CLOCK_50)
begin
	slot1 <= data_in;
	slot2 <= slot1;
	slot3 <= slot2;
	data_out <= slot3;
end

endmodule
	






module outputPort (CLOCK_50, data_out, credits_in, credit_out);
	
	/* put data to transmit here */
	/* this should look exactly like in the test bench for the queue */
	/* make sure to initialize the right number of credits*/
	reg credits[credit_width-1:0];
	reg last_addr;
	always @ (posedge CLOCK_50)
	begin
		last_addr <= addr;
		if(credits>0)
		begin
			addr <= (addr< addr_max)? addr+1'b1:addr;
		end
		else 
		begin
			addr <= addr;
		end
		
		
		if (credits_in) & (last_addr != addr)
		begin
			credits <= credits;
		end
		else if (credits_in) & (last_addr == addr)
		begin
			credits <= credits + 1'b1;
		end
		else if (~credits_in) & (last_addr != addr)
		begin
			credits <= credits - 1'b1
		end
		else if (~credits_in) & (last_addr == addr)
		begin
			credits <= credits;
		end
	end
	
	

endmodule

